1. Technical Field of the Invention
The present invention relates to the production of self-aligned barriers in microelectronics, for example, in integrated circuits.
2. Description of Related Art
Integrated circuits generally comprise barriers at the interface between a conducting region and an insulating region. The barriers prevent, for example, the diffusion of atoms from the conducting region into the insulating region.
FIG. 1 is a diagram of an example of a circuit portion according to the prior art. Conducting regions 1 and vias 2 are separated from a dielectric 5 by metal barriers 4 and by silicon nitride (Si3N4) barriers 3. The conducting regions 1 and the vias 2 are typically made of copper. The dielectric 5 may, for example, comprise fluorine-doped silicon oxide or FSG (fluorosilicate glass).
When a wafer of such a circuit is fabricated, the silicon nitride barriers 3 are deposited over the entire surface of the wafer. It is therefore necessary to carry out etching operations on the silicon nitride barriers 3 in order to create the places intended for the vias 2.
In addition, when a silicon nitride barrier is deposited over the entire surface of the wafer, as in the diagram shown in FIG. 1, the process is preceded by an initial copper deoxidation step. This is because copper oxide is relatively porous and brittle, facilitating the diffusion of copper atoms. Thus, when a relatively high current is applied to the circuit, there will be relatively weak retention of the copper atoms. Such a current may be applied so as to test the ageing resistance of the circuit. As a consequence, if the copper has not been correctly deoxidized before formation of the barrier, one ageing resistance characteristic of such a wafer risks being unsatisfactory.
U.S. Pat. No. 6,181,013 discloses a process for obtaining a layer comprising copper silicide molecules. A wafer comprising dielectric portions and copper portions on its surface is firstly cleaned. A plasma of nitrogen, ammonia and silane is then applied. This operation is carried out at about 400° C. This plasma results in the deposition of silicon nitride over the entire surface of the wafer. The silicon nitride deposited on the copper portions may react with the copper to form a layer comprising copper silicide molecules.
In applications of the imager type, light rays must pass through part of the circuit. Silicon nitride barriers distributed over the entire surface have the drawback that the light rays are partially refracted owing to the difference in optical index between the dielectric and the silicon nitride. This is because silicon nitride has a significantly higher optical index than the other dielectrics used.
FIG. 2 is a diagram of another example of a circuit portion according to the prior art. Conducting regions 1 and vias 2 are separated from a dielectric 5 by metal barriers 4 and by self-aligned barriers 6. The conducting regions 1 and the vias 2 are typically made of copper. The dielectric 5 may for example comprise FSG. The self-aligned barriers 6 are formed only on the copper.
The self-aligned barriers occupy only part of the surface of the wafer and thus prevent partial refraction of the light rays in imager applications.
The self-aligned barriers 6 may for example comprise silicon or cobalt.
When a self-aligned barrier comprising silicon is formed on copper, diffusion between copper atoms and silicon atoms of the self-aligned barrier generates a mixed copper silicide layer on the surface of the copper. This mixed layer allows better retention of the copper atoms when a relatively high current is applied to the circuit. Such a current may be applied so as to test the ageing resistance of the circuit. Consequently, a self-aligned barrier comprising silicon improves one ageing resistance characteristic of the circuit.
This advantage is also obtained with a self-aligned barrier comprising cobalt. This is because cobalt and copper only mix together at relatively high temperatures, above 422° C. A self-aligned barrier comprising cobalt therefore forms a good barrier to the diffusion of copper atoms. This barrier makes it possible to retain the copper atoms when a relatively high current is applied.
Self-aligned barriers comprising cobalt are fabricated by dipping the wafer into a solution. The solution reacts with copper, so that the barrier forms only on the surface of the copper. Such a process therefore requires the surface of the wafer to be prepared and certain parameters, such as the temperature and the pH, have to be controlled.
On the other hand, self-aligned barriers comprising silicon are relatively easy to produce, since their fabrication involves existing equipment.
The article “A novel self-aligned surface-silicide passivation technology for reliability enhancement in copper interconnects”, by T. Takewaki, 1995 Symposium on VLSI Technology Digest of Technical Papers, describes a process for forming a self-aligned barrier. A wafer is firstly cleaned by annealing at 500° C., and then silane is introduced with no plasma at a temperature between 150° C. and 200° C. The article specifies that this temperature could be up to 400° C. Copper acts as a catalyst in the reaction of decomposing silane to silicon, so that silicon is formed on the copper surface. The wafer then undergoes an annealing operation at 450° C. for 30 minutes so as to form a self-aligned copper silicide layer.
The article “Passivation of copper by silicide formation in dilute silane” by S. Hyme, Journal of Applied Physics, Vol. 71, pages 4623-4625, (1992), describes that the silicide layer may comprise molecules of formula Cu5Si, Cu15Si4 or even Cu3Si.
There is a need to further improve the ageing resistance characteristic.